Heterogeneous Integration of Electrical IC and Photonic IC (Co-Packaged Optics)

Level: Introductory Length: 4 hours Format: In-Person Lecture Intended Audience: Scientists, engineers, technicians, or managers who wish to learn more about heterogenous integration of EIC and PIC packaging. Undergraduate training in engineering or science is assumed. Description: This course explains basic principles and applications of heterogeneous integration of a switch, Electronic IC (EIC) and Photonic IC (PIC) packaging or co-packaged optics (CPO). A primary goal of the course is to reveal the fundamental, design, materials, process, fabrication, and reliability of switch, EIC and PIC packaging. Examples are taken from 3D stacking of EIC on PIC, heterogeneous integration of EIC and PIC with fan-out chip-last wafer-level and flip-chip bonding method, to heterogeneous integration of EIC and PIC with through-silicon via (TSV)-interposer and fiber coupling method. Anyone who wants to answer questions such as, “how to build heterogeneous integration of switch, EIC and PIC package?”, “how to make heterogeneous integration of PIC and EIC and switch on glass substrate? “how to stack EIC on PIC?”, “how to make hybrid bonding?”, “how to make microbump?”, “how to make fan-out package?”, “how to do flip chip packaging?”, or “how to make TSV-interposer?” will benefit from taking this course. Learning Outcomes: This course will enable you to: - design, materials, process, fabrication, and reliability of heterogeneous integration of EIC and PIC packaging or CPO - design, materials, process, fabrication, and reliability of 3D stacking EIC on PIC - design, materials, process, fabrication, and reliability of heterogeneous integration of switch, EIC and PIC with flip chip and fan-out packaging - design, materials, process, fabrication, and reliability of heterogeneous integration of switch, EIC and PIC with TSV-interposer packaging - design, materials, process, fabrication, and reliability of heterogeneous integration of switch, EIC and PIC on glass substrate - explain hybrid bonding technology - explain fan-out technology - explain surface mount technology - explain TSV-interposer technology - explain 3D IC stacking technology Instructor(s): John H. Lau has more than 40 years of R&D and manufacturing experiences in semiconductor packaging. He has published more than 528 peer-reviewed papers, 50 issued and pending U.S. patents, and 23 textbooks. He earned a Ph.D. in Theoretical and Applied Mechanics from the University of Illinois at Champaign-Urbana. Dr. Lau has been actively participating in industry, academic, and society meetings and conferences to contribute, learn, and share. He is a Fellow of ASME and IEEE. Event: SPIE Photonics West 2025 Course Held: 26 January 2025