Understanding Design-Patterning Interactions for EUV and DSA

Level: Intermediate Length: 4 hours Format: In-Person Lecture Intended Audience: Scientists, engineers, students, or managers who wish to learn more about how design and lithography interact. Undergraduate training in engineering or science is assumed. Description: EUV lithography and DSA haven been accepted by the industry as most promising candidates for dimensional scaling enablement at N7 technology node and beyond. This tutorial explains how introduction of such lithography technologies going to impact layout and circuit design. Choices of lithography would impact physical design and have a significant impact at system level. This tutorial will focus on transition from 193i multi-patterning technologies to EUV lithography and DSA. Factors that would determine on the enablement of these technologies would be highlighted and possible solutions would be shared. Learning Outcomes: This course will enable you to: - explain key aspects EUVL and DSA based design - determine how choice of patterning technology influences design rules - systematically evaluate what layers would be ideal candidate for EUVL and DSA - systematically evaluate hybrid DSA lithography schemes - examine defect avoidance methods for EUV - demonstrate the cost impact of these technologies, enabling factors for these technologies to be introduced in High volume manufacturing Instructor(s): Puneet Gupta is currently a faculty member of the Electrical Engineering Department at UCLA. He co-founded Blaze DFM Inc. in 2004 and served as its product architect till 2007. He has authored over 100 papers, 15 U.S. patents, a book and a book chapter. He is a recipient of IBM Faculty Award, NSF CAREER award, ACM/SIGDA Outstanding New Faculty Award, SRC Inventor Recognition Award. Dr. Puneet Gupta has given tutorial talks at DAC, ICCAD, SPIE Advanced Lithography Symposium, etc and served on several technical program committees. He currently leads the multi-university IMPACT+ Center (http://impact.ee.ucla.edu). Juan Andres Torres is currently the Advanced RET Flow Architect in the Design to Silicon Division focusing in the enablement of new resolution enhancement technologies such as EUV and Directed Self Assembly. He has been investigating the interactions between manufacturing process and electronic design flows to exploit areas of design and process co-optimization that provide more predictable and manufacture-friendly designs. He has published over fifty papers and holds several patents in the area of semiconductor manufacturing. Arindam Mallik works as a senior researcher in the Logic Technology department at imec. His group primarily works on Design Technology Co-optimization. He has published more than 30 papers in International Journals and Conferences and holds three patents. Dr. Mallik’s research interests include lithography-aware circuit design, cost modeling for semiconductor manufacturing, adaptive system architecture, and system-level analysis of advanced technology nodes. Event: SPIE Advanced Lithography 2018 Course Held: 27 February 2018