Lithography Integration for Semiconductor FEOL Fabrication

Level: Introductory Length: 4 hours Format: Online Intended Audience: This course is designed for engineers, technicians, and managers in FEOL/MOL/BEOL lithography development and manufacturing; scientists, engineers, managers, and technical support; and marketing and sales personnel of FEOL/MOL/BEOL lithographic material suppliers. It is also intended for those who have a general interest in semiconductor fabrication processes. Description: Semiconductor fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The FEOL integration is the part, which fabricates the primary element, i.e., devices, or transistors, in an integrated circuit. A typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. This course provides an overview of modern semiconductor FEOL integration fabrication process flow, its integration schemes, fabrication unit processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process, integration and lithography engineers a fundamental basis to develop materials and processes for FEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials, such as a variety of strain technologies, high-K/metal gate or HKMG, new devices, such as finFET, nanowires, GAA FET’s, Gate-All-Around Nano-sheet FET’s, as well as recent advances in lithography technology, such as self-aligned multipole patterning, EUV lithography. Complementary Lithography technology, and the advanced patterning trending from lithography technology domination to materials engineering domination. Learning Outcomes: This course will enable you to: - Module 0: Use your own words and phrases to describe the definition and basic concepts of lithography integrations for semiconductor Front-End-Of-Line (FEOL). - Point out and comprehend the 7 sub-sections of a typical FEOL integration. - Name and explain the three successful criteria of FEOL integration and the most key electric parameter in device power consumption. - Compose a 3D structure of a Metal-Oxide-Silicon Field Effect Transistor (MOC FET) in your mind - Identify the two key FET’s in CMOS and the key advantage of significantly limiting leak current in CMOS. - Module 1: Use your own words and phrases to describe the underline governing physics theory: the scaling theory, which has guided the semiconductor industries to have followed the Moore’s law for the last 40 years or so. - Identify the scalable parameters and the non-scalable parameters in the scaling theory. - Point out the two most critical process and materials technologies: strain technologies and metal high-k technologies, that the semiconductor industries invented and used to push the scaling forward after the conventional scaling technologies reached to the limit, such as SiO2 gate dielectric layer reached to it physical limit. - Name the two most important 3D FET’s structures: Gate-All-Around (GAA) FET and Gate-All-Around Nano-Sheet FET, after the FinFET’s. - Module 2: Comprehend the 6 key process flows in a typical FEOL integration flow and use your own words, phrases or diagrams to describe these key process flow, which can fabricate a typical poly silicon gate MOS FET in a step-by-step fashion. - Identify the 4 most critical technologies: conventional scaling technologies; strain technologies; metal high-k technologies, and FinFET technologies, that enabled the scaling trends of the semiconductor industries from 90nm to 7nm technology nodes. - Point out the most critical advantage of 3D FinFET’s, i.e., Short Channel Effect control, vs. planar MOS FET’s and the key electric parameters: parasitic capacitance associated with finFET structures, that do not advance for FinFET’s vs. planar MOS FET’s. - Name which generation of the technology node, i.e., 22nm, of which Intel introduced the FinFET technology and explain some of the key benefits of Intel FinFET’s vs. previous planar CMOS FET’s. - Module 3: Comprehend the key reasons, i.e.,193 nm immersion (193i) lithography technologies minimum resolutions are great than the minimum pitches of technology nodes, and explain why the advanced patterning technologies being adopted by the semiconductor industries. - Identify the 2 most critical process technologies: Etch and Atomic Layer Deposition (ALD) that paly critical roles in Self-Aligned Double Pattering (SADP). - Distinguish that materials engineering, e.g., Etch, Film, etc., have been becoming another equally critical driving force and technology similar as lithography technologies, such as 193i and EUV, for CMOS scaling, especially for enabling many critical self-aligned patterning schemes for continuously advancing scaling trends. - Compare the technology and physical limits and economic limiting factors in advanced patterning in continuously pushing the semiconductor industries moving forward. Instructor(s): Ying Zhang is currently the President of Naura America Inc., and was a vice president of Patterning Integration at Semiconductor Products Group (SPG), Applied Materials, Inc. His responsibilities include pathfinding, developing and implementing next-generation plasma source, chambers, and systems for etching and key integrated solutions into high volume manufacturing at advanced technology nodes. Prior to joining Applied, Dr. Zhang was a director with TSMC where he managed plasma etching and wet clean for 28 nanometer development and ramp-up to high volume manufacturing. He previously was at IBM’s T.J. Watson Research Center and led the development of dry etch and metallization technologies for multiple advanced nodes and exploratory novel device prototyping beyond the CMOS era. Dr. Zhang received a Ph.D. in physics. He has been recognized with various corporate awards, authored or co-authored more than 40 presentations and 100 publications, and holds over 100 issued patents. With Dr. Qinghuang Lin, Dr. Ying Zhang has been teaching the SC992: “Lithography Integration for Semiconductor FEOL/BEOL Fabrication” for more than 10 years as one of short courses offered by SPIE.