CMOS Image Sensors: Technology, Applications and Camera Design Methodology

Level: Introductory Length: 4 hours Format: In-Person Lecture Intended Audience: This course is for scientists, engineers, and managers involved with high performance CCD and CMOS imaging sensors and camera systems. A background in solid state electronics and physics is helpful but not necessary. Description:

This course provides an introductory to intermediate level overview of the theory and operation of CCD and CMOS image sensors with system design and application considerations in a half-day course. It has been updated to place more emphasis on CMOS and system design considerations with less emphasis on CCDs. A background in solid state electronics and physics is helpful but not necessary.

Topics include:

Basics of image capture/formation: photon capture, charge generation, movement and measurement.

Sensor architectures & operation, CCDs: full frame, frame transfer, interline and CMOS: Rolling Shutter, Progressive Scan and Global Snap Shutter. Frontside vs backside illumination. Operational differences between CCD and CMOS sensors.

Primary noise sources: signal shot noise, fixed pattern noise, thermal noise sources (dark shot noise, dark fixed pattern noise) and read noise plus CMOS random telegraph noise and image lag

Sensor/Camera performance characterization and noise and management: quantum efficiency, Fe55 Soft xray characterization / sensor diffusion MTF assessment/optimization, photon transfer analysis, SNR optimization

Sensor manufacturing: die size vs lithography type vs wafer size. Substrate electrical properties, Backside illumination fabrication differences. Laminated stacked die architectures.

System design considerations: tradeoffs among pixel architecture, pixel count, frame rate, pixel bit depth, sensor data bandwidth, electrical interfaces, frame buffering and network interface bandwidth.

Cost considerations: sensor size, frame rate, imaging optics, shuttering, cooling.

Imaging System Examples of Top Down Design Approach: Matching a camera to a target: specifying sensor type, pixel size, field of view, lens focal length/focal ratio, frame rate/exposure time, video vs still. Networked video camera high level design example using FPGA plus network interface: key elements, sample design calculations.

Learning Outcomes: This course will enable you to: - explain how CMOS image sensors convert light to images - list CMOS image sensor architectures - give examples of noise sources in images and options for mitigation - dissect an imaging system’s key performance parameters by measurement - explain important differences in image sensor manufacturing vs logic ICs - break down the steps of system design: selecting sensor architecture, pixel size, pixel count and optics - analyze cost tradeoffs for a camera design involving sensor size, optics, frame rate, etc. - design an imaging system using a top-down approach: networked video camera architectural example Instructor(s): Richard D. Crisp is currently vice president of new technology development and chief scientist for Etron America where he is engaged in developing low-cost DRAM architectures for miniaturized imaging systems. Mr. Crisp has designed Imaging Systems, CPUS, memories, and miniaturized semiconductor packaging. He has worked for Intel, Motorola, MIPS, Rambus, Tessera and Etron and has received over 107 patents for his work. He was a member of the ISSCC Program Committee from 1991 – 2000 serving as the Program Committee Chair in 2000, Vice Chair in 1999 and Memory Subcommittee Chair 1997-98. He has published many peer-reviewed papers in journals and conferences such as the ISSCC, IEEE JSSC, SPIE Electronic Imaging, ISMP, ICEP and IS&T including recent work published in the area of using Photon Transfer methods to quantify thermally-dependent image lag in cooled scientific imaging systems. Mr. Crisp is also an astro-photographer with many published images including with the OSA, Smithsonian and Space Telescope Science Institute. ---- Event: SPIE Photonics West 2025 Course Held: 28 January 2025