Lithography Integration for Semiconductor FEOL and BEOL Fabrication

Level: Introductory Length: 7 hours Format: In-Person Lecture Intended Audience: This course is designed for engineers, technicians, and managers in FEOL/MOL/BEOL lithography development and manufacturing; scientists, engineers, managers, and technical support; and marketing and sales personnel of FEOL/MOL/BEOL lithographic material suppliers. It is also intended for those who have a general interest in semiconductor fabrication processes. Description: Semiconductor fabrication, traditionally including Front-End-Of-the-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The BEOL processes include dielectric film deposition, patterning, metal fill and planarization by chemical mechanical polishing. The state-of-the-art semiconductor chips, the so called 7 nm node of Complementary Metal-Oxide-Semiconductor (CMOS) chips, in mass production features the fourth generation three dimensional (3D) FinFET, a minimum metal pitch of about 40 nm and copper (Cu)/low-k interconnects. It is the first generation of logic chips fabricated with extreme ultra-violet (EUV) lithography. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor fabrication process flow, its integration schemes, fabrication unit processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process, integration and lithography engineers a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high-K/metal gate or HKMG, III-V materials, non-copper BEOL metals), new device and interconnect structures (such as FinFET/ Trigate, nanowires, self-aligned via integration, Cu/air-gap interconnects) and new integrations (such as 3D IC, Through-Silicon Via or TSV, 3D heteogeneous integration) as well as recent advances in lithography technology (such as double patterning, EUV lithography and directed self-assembly, DSA). Implications of these FEOL, MOL and BEOL technologies for lithography will be discussed. Learning Outcomes: This course will enable you to: - acquire the critical concepts of modern semiconductor on-chip fabrication flow - review semiconductor technology trends - evaluate the basic concepts of FEOL/MOL/BEOL process integration flows - describe the basic processes of FEOL, including isolation, well doping, gate patterning, spacer, silicides and dual stress liner formation - identify the advanced patterning technology for scaling CMOS - describe how new materials and 3D COMS devices pose new challenges for lithography - identify the challenges and interactions between lithography and all the critical processes - describe BEOL copper/low-k dual damascene integration scheme - describe the basic processes used to fabricate dual damascene copper/low-k BEOL - examine the technical challenges in extending copper/low-k BEOL and Cu/air-gap interconnect integration - describe the basics of airgap interconnects, self-aligned BEOL copper/low-k dual damascene, and 3D heterogeneous integration scheme - review the unique requirements for BEOL lithography - develop lithographic materials and integration strategies for FEOL/MOL/BEOL patterning - demonstrate practical techniques for FEOL/MOL/BEOL lithography processes - examine recent innovations in semiconductor technology, including Cu/air-gap interconnects, non-copper BEOL metals, HKMG, FinFET, III-V, Nanowires, Double Patterning, DSA, 3D IC, heterogeneous integration, and TSV etc. - understand lithography implications of FEOL/MOL/BEOL technologies Instructor(s): Ying Zhang is a vice president of Patterning Integration at Semiconductor Products Group (SPG), Applied Materials, Inc. His responsibilities include path-finding, developing and implementing next-generation plasma source, chambers, and systems for etching and key integrated solutions into high volume manufacturing at advanced technology nodes. Prior to joining Applied, Dr. Zhang was a director with TSMC where he managed plasma etching and wet clean for 28 nanometer development and ramp-up to high volume manufacturing. He previously was at IBM's T.J. Watson Research Center and led the development of dry etch and metallization technologies for multiple advanced nodes and exploratory novel device prototyping beyond the CMOS era. Dr. Zhang received a Ph.D. in physics. He has been recognized with various corporate awards, participated in more than 40 presentations and 100 publications, and holds over 100 issued patents. Qinghuang Lin is Director of Technology Development Center at ASML, San Jose, California Previously he was a Research Staff Member, a Senior Manager and an IBM Master Inventor at IBM T.J. Watson Research Center. For more than 20 years, he has held positions in photoresist development, advanced lithography, BEOL materials & integration, 3D integration and semiconductor technology strategy and management for several nodes of CMOS technology research and development at IBM and ASML. He holds more than 100 issued US patents. Dr. Lin is the editor of 2 books and over 10 conference proceedings, and the author and co-author of over 80 technical papers. He is a co-recipient of several IBM Research Division Awards. He is an SPIE Fellow, ACS Fellow, PMSE Fellow and POLY Fellow. He chaired the SPIE Conference on Advances in Resist Materials and Processing Technology from 2006-2007 and Conference on Advanced Etch Technology from 2012-2013. Currently Dr. Lin serves as an associate editor of Journal of Micro/Nanolithography, MEMS and MOEMS (JM3). He has taught SPIE short courses for more than 10 years. Event: SPIE Advanced Lithography 2017 Course Held: 26 February 2017