Metrology of Image Placement

Level: Introductory Length: 4 hours Format: In-Person Lecture Intended Audience: Scientists, engineers, technicians, and managers in semiconductor and semiconductor equipment manufacturing who wish to learn about overlay control in IC manufacture, including technologies, issues, and methods in alignment, registration, and overlay metrology, with their expectations and applications environments, design and process interactions, integration, quality assurance, continuous improvement. Description: This course explains basic principles of metrology of image placement for applications to registration, alignment, and overlay in IC manufacture. Starting with IC Design Rules, and device pattern size and placement as their basis, this course outlines a systematic approach to dimensional metrology. Device pattern variation in mask-making, lithography imaging, image recoding, and image transfer, and down-stream wafer processing, are discussed leading to requirements of dimension metrology and control. Expectations in metrology of image placement are examined in the context of semiconductor design and manufacturing paradigm: device invariance in transformations of symmetry and translation, universal coordinate system, and absolute scale being the foundation of IC design. The same attributes built into IC design are maintained in production by the use of isoplanatic lithography systems, dimensionally stable masks, stages, and wafers, control of long distance scale and, of course, spatially uniform semiconductor processing. The key performance metrics for metrology of image placement are defined and illustrated in applications to improving robustness and accuracy in production environment. Systematic quantitative validation of those expectations for metrology systems and targets being measured, with complementary validation means and measurement technology, lay the foundation for certifiably accurate metrology of image placement and comprehensive control of overlay in IC manufacture. Learning Outcomes: This course will enable you to: - classify device pattern dimensions in terms of pitch, width or critical dimension (CD), centerline (CL), and layer-to-layer overlay (OL), and be able to participate in their physical definition for any process and layer as required by Design Rules (DRs) for device performance and yield - comprehend the complementary roles of CD and CL in the yield-limiting two-layer DRs for edge-to-edge overlay (a.k.a. separation, extension, overlap, enclosure etc.) - justify the need for DR budgeting, variance segmentation, and control of components of variance - distinguish applications environments in metrologies of pitch, placement, and critical dimension, and understand how those expectations define metrology tools and practices - define data analyses required, correctable vs. residual error, be ready for hands-on data analysis - review image- and diffraction-based approaches to metrology of image placement, expectations of metrology operability and performance, including precision, matching, and accuracy - establish the grounds for metrology error diagnostics and data culling, symmetry and redundancy based performance metrics, being different from, for example, error of response or residual of fit - explain the utility and the limitations of tool-induced shift (TIS) and wafer-induced shift (WIS) measurement performance metrics, what mechanisms drive them and how to reduce the impact - identify relevant SEMI standards and terminology, some technology- and company-specific measurement targets, basic target imaging, signal acquisition, and signal processing - become familiar with relevant SEMI standards and terminology, some technology- and company-specific measurement targets, basic target imaging, signal acquisition, and signal processing Instructor(s): Alexander Starikov Independent Consultant, has been developing lithography, alignment and overlay metrology for more than two decades, first at IBM Microelectronics in Fishkill, NY and then at Ultratech Stepper and Intel Corp. on the West Coast. His innovations in rule- and model-based OPC, lithography process monitors, alignment and overlay metrology have been widely adopted, with TIS/WIS performance metrics industry standard. He earned a Ph.D. in Physics from the University of Rochester, Rochester, NY. Dr. Starikov is a Fellow Member of SPIE. Event: SPIE Advanced Lithography 2016 Course Held: 21 February 2016