Interaction of Physical Design and Lithography

Level: Introductory Length: 4 hours Format: In-Person Lecture Intended Audience: This course is intended for lithography, OPC and mask engineers who want to learn physical design and its interaction with lithography. The attendees are expected to have a basic understanding (1-2yr experience) of how lithographic processing or OPC works. The attendees are not required to have prior training on physical design. Description: This course provides attendees with a basic knowledge of physical design and its interaction with lithography. Physical design covers a sequence of steps from logic synthesis, power planning, clock tree synthesis, placement, routing, timing closure, cell library creation and technology library creation. Each step has an impact on circuit layout and lithographic patterning. This is especially true when multiple patterning technology began to be adopted at 20nm and below. Based on the feedback of course attendees from previous years, we restrict the primary scope of physical design to four key topics- standard cells, placement, routing and timing closure, that are most relevant to lithographers. In this course, we will devote approximately 2/3 of the time to introducing the concept of physical design, and 1/3 of the time on its interaction with lithography. Also, the instructor will try to cover the physical design aspects relevant to the DPTCO papers to be presented in the conference later in the week. Learning Outcomes: This course will enable you to: - understand how multiple patterning affects standard cell design, placement, routing and timing closure - comprehend better the presentations and literatures, related to physical design, to be presented in the conference - describe the basic concept of placement, routing and timing closure in the design flow, and how standard cells are inserted into a design - decode a chip design into basic building blocks such as logic, memory, IO, etc - learn the basic interaction and trade-offs (e.g., large via enclosure vs routing resource) between physical design and lithography - explain the terminology (e.g., placement-induced litho hotspot, litho-aware routing, timing closure for multiple patterning) commonly used in the design-lithography world Instructor(s): Chi-Min (Chi) Yuan PhD has been involved in physical design, OPC and lithography throughout his 30 years in the industry, mostly through hands-on experiences. He obtained his PhD degree in Electrical and Computer engineering from Carnegie Mellon University. After graduation, he worked in IBM East Fishkill as a lithography engineer. He joined Motorola Austin and was assigned to SEMATECH to manage part of the phase shift mask program. Later, he led a process integration team to develop lithography processes in Motorola APRDL. He joined Precision Semiconductor Mask Corp. as a marketing director. In 2000, he joined Freescale (later acquired by NXP) Austin and led an engineering team to develop OPC technologies. In the past decade, he has been working in the areas of physical design, design for manufacturing and design enablement. Event: SPIE Advanced Lithography + Patterning 2023 Course Held: 27 February 2023